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preliminary data sheet w6694 passive usb - isdn s/t - controller - 1 - publication release date: march., 2000 revision 0.93 w6694 usb bus isdn s/t - controller data sheet
preliminary data sheet w6694 passive usb - isdn s/t - controller - 2 - publication release date: march., 2000 revision 0.93 the information described in this document is the exclusive intellectual property of winbond electronics corp and shall not be reproduced without permission from winbond. winb ond is providing this document only for reference purposes for w6694 - based system design. winbond assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice.
preliminary data sheet w6694 passive usb - isdn s/t - controller - 3 - publication release date: march., 2000 revision 0.93 table of contents 1. general descripti on ................................ ................................ ................................ ........... 5 2. features ................................ ................................ ................................ ................................ ... 5 3. pin configuration ................................ ................................ ................................ ................. 6 4. pin description ................................ ................................ ................................ ....................... 7 5. system diagram an d applications ................................ ................................ ................. 9 6.block diagram ................................ ................................ ................................ ...................... 10 7. functional descri ptions ................................ ................................ ................................ . 11 7.1 usb descriptions ................................ ................................ ................................ ................................ ....................... 11 7.1.1 control - in transactions (endpoint 0) ................................ ................................ ................................ .................. 11 7.1.1.1 get device descriptor ................................ ................................ ................................ ................................ ... 11 7.1.1.2 get configuration descriptor ................................ ................................ ................................ ........................ 12 7.1.1.3 get string descriptor 0 ................................ ................................ ................................ ................................ . 13 7.1.1.4 get string descriptor 1 (product) ................................ ................................ ................................ .................. 13 7.1.2 control - out tran sactions (endpoint 0) ................................ ................................ ................................ .............. 14 7.1.2.1 device clear feature, remote wake - up ................................ ................................ ................................ ........ 14 7.1.2.2 device set feature, remote wake - up ................................ ................................ ................................ ............ 14 7.1.2.3 set interface 0, alternate setting 1 ................................ ................................ ................................ ................ 14 7.1.2.4 set interface 0, alternate setting 0 ................................ ................................ ................................ ................ 14 7.1.3 bulk - out transaction (endpoint 1) ................................ ................................ ................................ .................... 14 7.1.4 bulk - in transaction (endpoint 2) ................................ ................................ ................................ ....................... 15 7.1.5 interrupt - in t ransaction (endpoint 3) ................................ ................................ ................................ ................. 15 7.1.6 isochronous - out transaction (endpoint 4) ................................ ................................ ................................ ........ 15 7.1.7 isochronous - in transaction (endpoint 5) ................................ ................................ ................................ ............ 17 7.1.8 suspend and resume ................................ ................................ ................................ ................................ ........... 18 7.2 configuration eeprom ................................ ................................ ................................ ................................ ............. 18 8. registe r descriptions ................................ ................................ ................................ ...... 19 8.1 interrupt registers ................................ ................................ ................................ ................................ ...................... 19 8.1.1 interrupt status register ista read_clear ................................ ................................ ................................ ..... 19 8.1.2 layer 1 command/indication register cir read ................................ ................................ ............................. 20 8.1.3 monitor channel interrupt status moir read_clear ................................ ................................ ....................... 20 8.1.4 pio input change register picr read_clear ................................ ................................ ................................ . 20 8.2 chip and fifo control registers ................................ ................................ ................................ ............................... 21 8.2.1 interru pt mask register imask read/write address 00h ................................ ................................ .............. 21
preliminary data sheet w6694 passive usb - isdn s/t - controller - 4 - publication release date: march., 2000 revision 0.93 8.2.2 command register 1 cmdr1 write address 01h ................................ ................................ ......................... 21 8.2.3 command register 2 cmdr2 write address 02h ................................ ................................ ......................... 22 8.2.4 control register ctl read/write address 03h ................................ ................................ ............................ 22 8.2.5 layer 1 command/indication regis ter cix read/write address 04h ................................ ............................... 23 8.2.6 u - layer1 ready code l1_rc read/write address 05h ................................ ................................ ................... 23 8.3 gci mode registers ................................ ................................ ................................ ................................ ................... 23 8.3.1 gci mode command register gcr read/write address 06h ................................ ................................ ......... 23 8.3.2 monitor channel control register mocr read/write address 07h ................................ ................................ . 24 8.3.3 monitor channel receive register mor read address 08h ................................ ................................ .......... 25 8.3.4 monitor channel transmit register mox read/write addres s 09h ................................ ................................ . 25 8.4 programmable io registers ................................ ................................ ................................ ................................ ........ 25 8.4.1 pio input enable register pie read/write address 0ah ................................ ................................ ................ 25 8.4.2 pio output register 1 po1 read/write address 0bh ................................ ................................ .................... 25 8.4.3 pio output register 2 po2 read/write address 0ch ................................ ................................ .................... 26 8.4.4 pio data register pdata read address 0dh ................................ ................................ .............................. 26 8.5 b channel switch registers ................................ ................................ ................................ ................................ ....... 26 8.5.1 layer1 b1 receiver select register l1b1rs read/write address 0eh ................................ ............................ 26 8.5.2 layer1 b2 receiver select register l1b2rs read/write address 0fh ................................ ............................ 26 8.5.3 usb b1 receiver select register usbb1rs read/write address 10h ................................ ............................. 27 8.5.4 usb b2 receiver select register usbb2rs read/write address 11h ................................ ............................. 27 8.5.5 pcm1 receiver select register pcm1rs read/write address 12h ................................ ................................ . 27 8.5.6 pcm2 receiver select register pcm2rs read/write address 13h ................................ ................................ . 28 9. electrical charac teristics ................................ ................................ .......................... 28 9.1 absolute maximum rating ................................ ................................ ................................ ................................ ......... 28 9.2 power supply ................................ ................................ ................................ ................................ ............................. 28 9.3 dc characteristics ................................ ................................ ................................ ................................ ..................... 29 9.4 preliminary switching characteristics ................................ ................................ ................................ ........................ 30 9.4.1 pcm interface timing ................................ ................................ ................................ ................................ ......... 30 9.4.2 serial eeprom timing ................................ ................................ ................................ ................................ ...... 32 list of figures fig.3.1 w6694 pin out ................................ ................................ ................................ ................................ ...................... 6 fig 6.1 w6694 block diagram ................................ ................................ ................................ ................................ ... 10 list of tables table 4.1 w6694 pin descriptions ................................ ................................ ................................ ............................. 7 table 7.1 w6694 all usb endpoints ................................ ................................ ................................ ....................... 11
preliminary data sheet w6694 passive usb - isdn s/t - controller - 5 - publication release date: march., 2000 revision 0.93 1. general descripti on the winbond ' s single chip usb bus isdn s/t interface controller w6694 is an all - in - one device suitable for isdn internet access. the integrated usb and isdn design provides low cost, pure passive solution for usb - idsn application. w6694 also provides two pcm codec interfaces for the ability to access isdn through voi ce channel. 2. features isdn features full duplex 2b+d s/t - interface transceiver compatible with itu - t i.430 recommendation four wire operation received clock recovery layer 1 activation/deactivation procedure d channel access control transparent data tra nsmission of 2b+d channels test functions usb features usb specification version 1.0/1.1 compliant full - speed, bus - powered usb device integrated transceiver, pll, sie, sil, and voltage regulator built - in fully automatic enumeration procedure support suspe nd mode suspend current requirement wake - up by isdn (remote) and pc (host) other feature gci bus interface (slave mode) for connecting to isdn u transceiver chip. pcm port provides two 64k clear channels to connect to pcm codec chips. b channel data switc hing function for selective connection between isdn/gci interface, usb, and pcm. eeprom interface for retrieving customized usb device identification data. io pins with led current drive capability. reset pin for whole - chip reset.
preliminary data sheet w6694 passive usb - isdn s/t - controller - 6 - publication release date: march., 2000 revision 0.93 3. pin configuration 37 38 36 35 34 33 32 31 30 29 28 27 26 25 39 40 41 43 42 44 45 46 47 48 24 23 22 21 20 18 19 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 vddu d+ d - vdd3 uclk1 v s s u n c s u s p # i o p 7 i o p 6 i o p 5 i o p 4 i o p 3 i o p 2 i o p 1 i o p 0 r e s e t # uclk2 vdd3i vss1 sr1 sr2 vdd1 sx1 vdd23 vss23 test2# test1# epdo epdi epsk epcs prxd ptxd vdd22 vss22 s x 2 x t a l 1 x t a l 2 v s s 2 1 v d d 2 1 g c i d c l g c i f s c g c i d d g c i d u p f c k 1 p f c k 2 p b c k fig.3.1 w6694 pin o ut
preliminary data sheet w6694 passive usb - isdn s/t - controller - 7 - publication release date: march., 2000 revision 0.93 4. pin description table 4.1 w6694 pin descriptions note : the suffix # indicates active low signal. symbol pin no. i/o function usb bus d+ 38 i/o usb d+ data line. d - 39 i/o usb d - data line. uclk1 41 i 24 mhz crystal/oscillator clock input. uclk2 42 o 24 mhz crystal clock output. left unconnected if use oscillator. isdn signals and external crystal sr1 45 i s/t bus receiver input ( - ). this is normal polarity. reverse polarit y is also ok. sr2 46 i s/t bus receiver input (+). sx1 48 o s/t bus transmitter output(+). sx2 1 o s/t bus transmitter output( - ). xtal1 2 i crystal or oscillator clock input. the clock frequency: 7.68mhz 100ppm. xtal2 3 o crystal clock output. left un connected when using oscillator. gci bus gcidcl 6 i gci bus data clock 1.536 mhz. gcifsc 7 i gci bus frame synchronization clock. gcidd 8 i gci bus data downstream. (input) gcidu 9 o gci bus data upstream. (output) pcm bus pfck1 10 o pcm port 1 fram e synchronization signal with 8 khz repetition rate and 8 bit pulse width pfck2 11 o pcm port 2 frame synchronization signal with 8 khz repetition rate and 8 bit pulse width pbck 12 o pcm bit clock of 1.536 mhz. ptxd 15 o pcm data output. prxd 16 i p cm data input. external serial eeprom interface epcs 17 o serial eeprom chip select. epsk 18 o serial eeprom data clock. epdi 19 i serial eeprom data input epdo 20 o serial eeprom data output power and ground vdd1,vss1 47,44 i isdn s/t analog pow er (5v), ground vdd21,vss21 5,4 i digital power (5v), ground
preliminary data sheet w6694 passive usb - isdn s/t - controller - 8 - publication release date: march., 2000 revision 0.93 vdd22,vss22 vdd23,vss23 14,13 24,23 vddu,vssu 37,36 i usb core power (5v), ground vdd3 40 o regulator output (3.3v) vdd3i 43 i regulator input (3.3v) io pins iop0 iop1 iop2 iop3 iop4 iop5 i op6 iop7 26 27 28 29 30 31 32 33 i/o i/o i/o i/o i/o i/o i/o i/o io pin capable of driving led. others reset# 25 i external reset. cause internal circuit reset and usb re - enumeration. test1#,test2# 21,22 i test mode enable. connected to high for nor mal operation. susp# 34 o usb suspended. nc nc 35 no connection.
preliminary data sheet w6694 passive usb - isdn s/t - controller - 9 - publication release date: march., 2000 revision 0.93 5. system diagram an d applications typical applications include : usb passive ta for data only service usb passive ta with one data plus one voice
preliminary data sheet w6694 passive usb - isdn s/t - controller - 10 - publication release date: march., 2000 revision 0.93 6. block diagram fig 6.1 w6694 block diagram isdn transceiver & layer 1 function usb transceiver & sie & function pcm port control b uffer eeprom control usb bus serial eeprom interface b channel switch b b gci control serial interface b gci bus s/t interface pcm codec interface 2b+d io port control io port
preliminary data sheet w6694 passive usb - isdn s/t - controller - 11 - publication release date: march., 2000 revision 0.93 7. functional descri ptions 7.1 usb descriptions table 7.1 w6694 all usb endpoints end point type direction* max. packet size (bytes) internal b uffer type and size (bytes) 0 control in/out 8/8 8, single port x 2 1 bulk out 8 8, single port x 1 2 bulk in 8 8, single port x 1 3 interrupt in 5 5, single port x 1 4 isoch. out (1+3) + (1+18) = 23 96, dual port x 1 5 isoch. in 1+ (1+7) + (1+15) + (1+15) = 41 96, dual port x 1 * direction: in ? device to host, out ? host to device usb standard requests are supported by w6694, and w6694 will respond to requests according to usb specification revesion 1.1. these includes ? clear_feature, get_confi guration, get_descriptor, get_interface, get_status, set_address, set_configuration, set_descriptor, set_feature, set_interface ? . the ? sync_frame ? request is not supported. 7.1.1 control - in transactions (endpoint 0) 7.1.1.1 get device descriptor offset field size default value (hex) updated by eeprom 0 blength 1 12 1 bdescriptortype 1 01 2 bcdusb 2 0110 4 bdeviceclass 1 00 5 bdevicesubclass 1 00 6 bdeviceprotocol 1 ff 7 bmaxpacketsize 1 08 8 idvendor 2 1046 yes * 10 idproduct 2 6694 yes * 12 bcddevice 2 0100 yes * 14 imanufacturer 1 00 15 iproduct 1 01
preliminary data sheet w6694 passive usb - isdn s/t - controller - 12 - publication release date: march., 2000 revision 0.93 16 iserialnumber 1 00 17 bnumconfiguration 1 01 * note: refer to eeprom session for its layout of contents. 7.1.1.2 get configuration descriptor offset field size value (hex) r emark configuration descriptor 0 blength 1 09 1 bdescriptortype 1 02 2 wtotallength 2 003e 62 4 bnuminterface 1 01 5 bconfigurationvalue 1 01 6 iconfiguration 1 00 7 bmattributes 1 a0 bus powered, remote wakeup 8 maxpower 1 32 100 ma interfa ce 0 descriptor 0 blength 1 09 1 bdescriptortype 1 04 2 binterfacenumber 1 00 3 balternatesetting 1 00 4 bnumendpoints 1 00 5 binterfaceclass 1 00 6 binterfacesubclass 1 00 7 binterfaceprotocol 1 ff 8 iinterface 1 00 alternate interface 0 descriptor 0 blength 1 09 1 bdescriptortype 1 04 2 binterfacenumber 1 00 3 balternatesetting 1 01 4 bnumendpoints 1 05 5 binterfaceclass 1 00 6 binterfacesubclass 1 00 7 binterfaceprotocol 1 ff 8 iinterface 1 00 endpoint 1 descriptor 0 blength 1 07 1 bdescriptortype 1 05 2 bendpointaddress 1 01 out 3 bmattributes 1 02 bulk 4 wmaxpacketsize 2 0008
preliminary data sheet w6694 passive usb - isdn s/t - controller - 13 - publication release date: march., 2000 revision 0.93 6 binterval 1 00 endpoint 2 descriptor 0 blength 1 07 1 bdescriptortype 1 05 2 bendpointaddress 1 82 in 3 bmattributes 1 02 b ulk 4 wmaxpacketsize 2 0008 6 binterval 1 00 endpoint 3 descriptor 0 blength 1 07 1 bdescriptortype 1 05 2 bendpointaddress 1 83 in 3 bmattributes 1 03 interrupt 4 wmaxpacketsize 2 0005 6 binterval 1 01 endpoint 4 descriptor 0 blength 1 07 1 bdescriptortype 1 05 2 bendpointaddress 1 04 out 3 bmattributes 1 01 isochronous 4 wmaxpacketsize 2 0017 6 binterval 1 01 endpoint 5 descriptor 0 blength 1 07 1 bdescriptortype 1 05 2 bendpointaddress 1 85 in 3 bmattributes 1 01 isochron ous 4 wmaxpacketsize 2 0029 6 binterval 1 01 7.1.1.3 get string descriptor 0 offset field size value (hex) description 0 blength 1 04 1 bdescriptortype 1 03 2 wlanguage id 2 0409 u.s. english 7.1.1.4 get string descriptor 1 (product) offset field size (hex) value (hex) string (unicode) 0 blength 1 18 1 bdescriptortype 1 03 2 bstring 16 ? usb isdn ta ?
preliminary data sheet w6694 passive usb - isdn s/t - controller - 14 - publication release date: march., 2000 revision 0.93 7.1.2 control - out transactions (endpoint 0) 7.1.2.1 device clear feature, remote wake - up bmrequesttype brequest wvalue windex wlength data 00h clear_feature 1 0 0 none on received this request from host, w6694 will not detect the incoming isdn broadcast message. 7.1.2.2 device set feature, remote wake - up bmrequesttype brequest wvalue windex wlength data 00h set_feature 1 0 0 none on received this request from host, w6694 will detect the incoming isdn broadcast message. this is default setting. 7.1.2.3 set interface 0, alternate setting 1 bmrequesttype brequest wvalue windex wlength data 01h set_interface 0 0 0 none on recei ved this request from host, w6694 will reset and disable the d/b1/b2 channel xfifo and rfifo. this is default setting. 7.1.2.4 set interface 0, alternate setting 0 bmrequesttype brequest wvalue windex wlength data 01h set_interface 1 0 0 none on rec eived this request from host, w6694 will enable the d/b1/b2 channel xfifo and rfifo. 7.1.3 bulk - out transaction (endpoint 1) bulk - out endpoint is used to write data to register or/and index which register to be read in following bulk - in transaction. a pare of two bytes (address, data) in bulk - out data packet represents a read or write command on one
preliminary data sheet w6694 passive usb - isdn s/t - controller - 15 - publication release date: march., 2000 revision 0.93 register. a maximum of 8 bytes consist one bulk - out transaction. w6694 perform the read/write commands following their order in the packet. data packet fo r bulk - out transaction: offset 0 1 2 3 4 5 6 7 address1 data1 address2 data2 address3 data3 address4 data4 address byte will indicate the read or write action to that register, by assigning highest order bit (bit 7) to 0 (read) or 1 (write). contents of address byte: bit 7 6 5 4 3 2 1 0 0/1 0 0 a4 a3 a2 a1 a0 bit 7: 0/1 = read/write bit 4 - 0: address offset of register. the data byte is the write data (write operation) or 00h (read operation). 7.1.4 bulk - in transaction (endpoint 2) bulk - in endpoin t is for retrieving register data of w6694. it returns the registers data that are requested by most recent bulk - out data - read request. inside the data packet, one register occupies 2 bytes. the first is register ? s offset address, the 2 nd byte is date. a maximum of 4 register data can be sent to host in one bulk - in packet. offset 0 1 2 3 4 5 6 7 address1 data1 address2 data2 address3 data3 address4 data4 7.1.5 interrupt - in transaction (endpoint 3) interrupt - in endpoint is used to periodically poll device interrupt data. w6694 use this endpoint to report interrupt status of all interrupt sources. all four bytes data of interrupt registers will be sent to host if ista is not 0. if no interrupt is detected by w6694 when received interrupt - in token, a nak token will return to usb host. data packet for interrupt - in transaction: offset 0 1 2 3 4 ista cir picr pdata moir 7.1.6 isochronous - out transaction (endpoint 4) after power - on or hardware reset, all b and d channels transmit fifo (xfifo) are disabled. a disabled xfifo can not receive data from usb. but the transmitter will automatically send inter frame time fill pattern (all 1 ? s) to isdn
preliminary data sheet w6694 passive usb - isdn s/t - controller - 16 - publication release date: march., 2000 revision 0.93 interface. the disabled xfifo can be enabled by command xen on each channel. an enabled xfifo can re ceive data from usb, and send data to usb host. software decides the size of data to transmit depending on available xfifo space, which is indicated by xfr flag carried by isochronous - in packet. when xfr is reported to host, it means that xfifo has at le ast half of the total xfifo size available for that channel. each channel has its own xfifo and status flags. if the incoming isochronous - out packet is detected error, some action will be automatically taken for d and b channel xfifo. for d channel, the xfifo is reset and automatically enabled. for b channel, the xfifo are not reset, and the data remained in xfifo are still valid and will be transmitted to isdn later. but the new incoming b channel data will be replaced by ffh, and stored into xfifo. t he continuous ffh will later be transmitted to corresponding b channel of isdn interface. this isochronous - out packet error will be reported to host, by setting bit isoe of isochronous - in packet to 1. d channel fifo will recognize and only accept data w ithin hdlc frame (including opening and closing flag), all other data outside hdlc frame are ignored and not stored in fifo. b channel fifo accept any data after it is enabled. the packet format of isochronous - out is as below: bit 7 6 5 4 3 2 1 0 d_len1 d_len0 d_data (1 st byte) d_data (2 nd byte) d_data (3 rd byte) b_len3 b_len2 b_len1 b_len0 b1_data ... b2_data ... d_len1 - 0 d channel data length these bits indicate the data length of the subsequent data for d channel. the length shou ld be from 1 and 3 bytes inclusively, otherwise a transmit fifo under - run or overflow condition may occur. the valid data are hdlc frame, including opening and closing flag (7eh), and bit - stuffed data in between. note that software should transmit the fi rst data byte as opening flag in byte (8 - bits) boundary. due to the nature of hdlc framing, the closing flag may not be in byte - boundary. software should stuff the remaining bit positions (if any) with binary ? 1 ? , to fill the last byte, unless the last b yte is 7eh. d_d ata d channel data these are d channel data space, which always occupy 3 bytes in the packet. software should put actual data length in d_len. if the data length is less then 3, the remaining bytes position should fill with ffh. b_len3 - 0 b channel data length these bits indicate the data length of subsequent data for each b channel. the length should be from 7 to 9 bytes inclusively, otherwise a transmit fifo under run or overflow condition may occur. note that two b channels have same data length. b1_data b1 channel data these are b1 channel data, the length is indicated by b_len. b2_data b2 channel data these are b2 channel data, the length is indicated by b_len.
preliminary data sheet w6694 passive usb - isdn s/t - controller - 17 - publication release date: march., 2000 revision 0.93 7.1.7 isochronous - in transaction (endpoint 5) after power on or res et, all b and d channels receive fifo (rfifo) are disabled. a disabled rfifo can not receive data from isdn, and will always return zero - length data for isochronous - in transaction. rfifo can only be enabled by command cmdr:ren. once enabled, an isochro nous - in transaction can read data from rfifo of that channel. the data packet also carries xfifo status for that channel, and the most recent isochronous - out packet error status (if error ever occurred). the packet format of isochronous - in is as below: bit 7 6 5 4 3 2 1 0 isoe d_xfr d_xcol d_xdov d_xdun d_rdov d_len2 d_len1 d_len0 d_data ... b1_xfr b1_xdov b1_xdun b1_rdov b1_len3 b1_len2 b1_len1 b1_len0 b1_data ... b2_xfr b2_xdov b2_xdun b2_rdov b2_len3 b2_len2 b2_len1 b2_len0 b2_data .. . isoe isochronous - out error this bit is set to indicate that the most recent received isochronous - out packet has crc error. this bit will remain set, until a cmdr1:cisoe clears it. xcol transmit collision (d channel only) this bit indicates a d chann el collision on the s - bus has been detected. the data in d channel xfifo will be automatically re - transmitted, until the whole hdlc frame are successfully transmitted. this bit will remain set, until software issue cmdr1:dxen to clear this bit. xfr tr ansmit fifo ready it is set when xfifo has at least half of the xfifo size available for incoming usb data. xdun transmit data under - run the corresponding xfifo has run out of data. for d and b channel, the xfifo is reset and disabled for that channel. this bit is cleared when xfifo is enabled by xen bit. xdov transmit data overflow the corresponding xfifo has overflow condition. data in xfifo are overwritten by incoming usb data. for d and b channel, the xfifo is reset and disabled for that channel . this bit is cleared when xfifo is enabled by xen bit. rdov receive data overflow the corresponding rfifo has overflow condition. data in rfifo are overwritten by incoming isdn data. when overflow condition occurred, the d and b channel rfifo is rese t and disabled for that channel. this bit is cleared when rfifo is enabled by ren bit.
preliminary data sheet w6694 passive usb - isdn s/t - controller - 18 - publication release date: march., 2000 revision 0.93 7.1.8 suspend and resume w6694 supports usb suspend and resume function as described in usb specification 1.1. when there is more than three millisecond period of in activity on the usb, w6694 will automatically enter into a low - power suspend state. in this state, most of the isdn and usb module will be powered off to consume minimum power. but the internal register values are preserved. therefore it is recommended that the software perform necessary control to w6694 before power - down. the w6694 will leave suspend mode only when one of the two condition happens: host or device wake - up. a ista:wake bit will indicate to software which source the wake - up event is orig inated from. (i). host - initiated wake - up the usb host may wake - up w6694 by sending traffic on usb. on detected this wake - up signal, w6694 will automatically resume to normal operation. (ii). device remote wake - up in suspend mode, w6694 will ignore any i sdn traffic on s/t bus, except for incoming broadcast messages. when there is an incoming broadcast message from isdn switch, such as setup message, w6694 will automatically wake - up, and signal usb host that it has left suspend mode. the first few bytes of setup message will be saved in d channel rfifo. after returning from suspend mode, software should immediately read the rfifo, and perform necessary operation as specified in isdn protocol. 7.2 configuration eeprom a 9346/93c46 type serial eeprom can be used to store customized usb device configuration data. these configuration data will be read by w6694 after power on or reset, and sent to usb host during enumeration. if eeprom is not presented, or the first 16 bits in eeprom is ffffh, the default value in w6694 will be sent to usb host instead. eeprom wire connection : eeprom contents : w6694 eeprom epcs epcs epsk epdo ep di chip select data in data out serial clock
preliminary data sheet w6694 passive usb - isdn s/t - controller - 19 - publication release date: march., 2000 revision 0.93 offset size (byte) contents 15 0 0 2 vendor id 2 2 device id 4 2 device rel ease number 8. register descript ions 8.1 interrupt registers these registers will be read by interrupt - in packet only, so usb host will periodically receive these data. these registers can not be read by bulk - in transfer. 8.1.1 interrupt status register ista read_clear this register indicates interrupt occurred in various interrupt sources. this register is cleared automatically after it is read and successfully acked by usb host. values after reset: 00h 7 6 5 4 3 2 1 0 icc moc pi oic 0 0 0 0 wake icc layer 1 indication code change a change of value in the received indication code has been detected. the new code is in layer 1 command/indication register (cir) register. moc monitor channel status change a change of value in the g ci mode monitor channel interrupt register (moir) has occurred. pioic programmable io port input signal changed a change of value in at least one input io pin is detected. the input io pins that change value can be identified in pio input change register (picr) register. wake device remote wake - up this bit indicates that w6694 has left suspend mode by detecting a broadcast setup message from isdn switch. d channel receive fifo (rfifo) has buffered the first few bytes of setup message. software should issue isochronous - in transaction to read this message.
preliminary data sheet w6694 passive usb - isdn s/t - controller - 20 - publication release date: march., 2000 revision 0.93 8.1.2 layer 1 command/indication register cir read value after reset: 0fh 7 6 5 4 3 2 1 0 0 0 0 0 cir3 cir2 cir1 cir0 cir3 - 0 layer 1 indication code value of the received layer 1 indication code for s/t interface. note these bits have a buffer size of two. note : if s/t layer 1 function is disabled and gci bus is enabled (ge=1 in gcr register), cir register is used to receive layer 1 indication code from u transceiver. in this case, the supported indication codes are : indication symbol code descriptions deactivation confirmation dc 1111 idle code on gci interface power up indication pu 0111 u transceiver power up 8.1.3 monitor channel interrupt status moir read_clear value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 mdr mer mda mab mdr monitor channel data receive mer monitor channel end of reception mda monitor channel data acknowledged mab monitor channel data abort 8.1.4 pio input change register picr read_clear value after reset: 00 h 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 p7 - 0 indicator of io pin input status 0: this io pin is either output pin, or did not change input value. 1: this io pin changed value. note : registers in sections 8.2 to 8.5 are written/read by bulk - out/bul k - in transactions.
preliminary data sheet w6694 passive usb - isdn s/t - controller - 21 - publication release date: march., 2000 revision 0.93 8.2 chip and fifo control registers 8.2.1 interrupt mask register imask read/write address 00h value after reset: e1h 7 6 5 4 3 2 1 0 icc moc pioic 0 0 0 0 wake setting ? 1 ? to each bits masks the corresponding interrupt sources in ista register. 8.2.2 command register 1 cmdr1 write address 01h value after reset: 00h writing 1 to the following bits will activate each corresponding function. writing 0 to these bits has no effect. 7 6 5 4 3 2 1 0 dxrst drrst dxen dren srst ci soe dlp rlp dxrst d channel transmitter reset setting this bit resets d channel transmitter, and clear transmit fifo (xfifo). the transmitter will immediately transmit inter frame time fill pattern (all 1 ? s) to d channel in isdn layer 1, but the xfifo i s disabled (not active). software must issue dxen to enable (activate) d channel xfifo. after reset is done, this bit becomes 0. if this bit and other bits are set at the same time, the reset action will be performed first and completed, then other acti ons will follow. drrst d channel receiver reset setting this bit resets d channels receiver, and clear receive fifo (rfifo). the d channels is disabled (not active). software must issue dren to enable (activate) d channel rfifo, in order to receive d ch annel data from isdn, and send data to usb. after reset is done, this bit becomes 0. if this bit and other bits are set at the same time, the reset action will be performed first and completed, then other actions will follow. dxen d channel transmit fi fo enable setting this bit enables d channel transmit fifo (xfifo). after enabled, the d channel xfifo will begin to receive d channel data from usb, and send data to isdn. after enabled, this bit becomes 0. dren d channel receive fifo enable setting th is bit enables d channel receive fifo (rfifo). after enabled, the d channel rfifo will begin to receive d channel data from isdn, and send data to usb. after enabled, this bit becomes 0. srst software reset setting this bit internally generates a softwa re reset signal. the effect of this reset signal is equivalent to hardware reset pin, except that the usb circuit and all usb configured data are not reset. after reset is done, this bit becomes 0. this bit must be set along, i.e., all other bits in thi s register must not set at the same time. cisoe clear isochronous - out error
preliminary data sheet w6694 passive usb - isdn s/t - controller - 22 - publication release date: march., 2000 revision 0.93 setting this bit clears error indication bit isoe of isochronous - out error. this bit is carried by isochronous - in packet. after bits are cleared, this bit becomes 0. dlp dig ital loopback setting this bit activates the digital loopback function. the transmitted digital 2b+d channels are looped to the received 2b+d channels. note that after hardware reset, the internal clocks will turn off if the s bus is not connected or if th ere is no signal on the s bus. in this case, the c/i command eck must be issued to enable loopback function. this bit remains set, until cleared by software reset (srst). rlp remote loopback setting this bit activates the remote loopback function. the received 2b channels from the s interface are looped to the transmitted 2b channels of s/t interface. the d channel is not looped in this loopback function. this bit remains set, until cleared by software reset (srst). 8.2.3 command register 2 cmdr2 wr ite address 02h value after reset: 00h bits in this register act similar to that of cmdr1 register, except that the effect is on b1 or b2 channel xfifo/rfifo, instead of on d channel xfifo/rfifo. 7 6 5 4 3 2 1 0 b1xrst b1rrst b1xen b1ren b2xrst b2rrst b2xen b2ren b1xrst b1 channel transmitter reset b1rrst b1 channel receiver reset b1xen b1 channel transmit fifo enable b1ren b1 channel receive fifo enable b2xrst b2 channel transmitter reset b2rrst b2 channel receiver reset b2xen b2 channel transmit fifo enable b2ren b2 channel receive fifo enable 8.2.4 control register ctl read/write address 03h value after reset : 00h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ops1 ops0 ops1 - 0 output phase delay compensation select1 - 0 these two bits select the output phase delay compensation. ops1 ops0 effect 0 0 no output phase delay compensation 0 1 output phase delay compensation 260ns
preliminary data sheet w6694 passive usb - isdn s/t - controller - 23 - publication release date: march., 2000 revision 0.93 1 0 output phase delay compensation 520 ns 1 1 output phase delay compensation 1040 ns 8.2.5 layer 1 command/indication regi ster cix read/write address 04h value after reset: 0fh 7 6 5 4 3 2 1 0 0 0 0 0 cix3 cix2 cix1 cix0 cix3 - 0 layer 1 command code value of the command code transmitted to layer 1. a read to this register returns the previous written value. note : if s/t layer 1 function is disabled and gci bus is enabled (ge=1 in gcr register), cix register is used to issue layer 1 command code to u transceiver. in this case, the supported command code is: command symbol code descriptions activate request command ar 10 00 activate request command 8.2.6 u - layer1 ready code l1_rc read/write address 05h value after reset: 0ch 7 6 5 4 3 2 1 0 0 0 0 0 rc3 rc2 rc1 rc0 rc3 - 0 ready code when gci bus is being enabled, these four programmable bits are allowed to progra m different layer 1_ready code (ai: activation indication) by user. for example: siemens peb2091: ai=1100, motorola mc145572: ai=1100. 8.3 gci mode registers 8.3.1 gci mode command register gcr read/write address 06h value after reset: 00h 7 6 5 4 3 2 1 0 mac 0 0 tlp grlp spu pd ge mac monitor transmit channel active (read only) data transmission is in progress in gci mode monitor channel. 0: the previous transmission has been terminated. before starting a transmission, software should verify that t he transmitter is inactive.
preliminary data sheet w6694 passive usb - isdn s/t - controller - 24 - publication release date: march., 2000 revision 0.93 1: the previous transmission is in progress. tlp test loopback when set this bit both the gcidu and gcidd lines are internally connected together. the gci mode loopback test function: gcidu is internally connected with gcidd, e xternal input on gcidd is ignored. grlp gci mode remote loopback setting this bit to 1 activates the remote loopback function. the 2b+d channels data received from the gci bus interface are looped to the transmitted channels. spu software power up pd pow er down spu pd description 0 1 after u transceiver power down, w6694 will receive the indication dc (deactivation confirmation) from gci bus and then software has to set spu ? 0, pd ? 1 to acknowledge u transceiver, by pulling gcidu line to high. w66 94 remains normal operation. 1 0 setting spu ? 1, pd ? 0 will pull the gci bus gcidu line to low. this will enforce connected layer 1 devices (u transceiver) to deliver gci bus clocking. 0 0 after reception of the indication pu (power up indication) the r eaction of the microprocessor should be: - to write an ar (activate request command) as c/i command code in the cix register. - to reset the spu bit and wait for the following icc (indication code change) interrupt. 1 1 unused. ge gci mode enable sett ing this bit to 1 will enable the gci bus interface. in the same time, the s/t layer 1 function is disabled. 8.3.2 monitor channel control register mocr read/write address 07h value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 mrie mrc mxie mxc mrie monitor channel 0 receive interrupt enable monitor channel interrupt status mdr, mer generation is enabled (1) or masked (0). mrc mr bit control determines the value of the mr bit: 0: mr bit always 1. in addition, the mdr interrupt is blocked, except for the first byte of a packet (if mrie=1). 1: mr internally controlled according to monitor channel protocol. in addition, the mdr interrupt is enabled for all bytes according to the monitor channel protocol (if mrie=1). mxie monitor channel transm it interrupt enable monitor interrupt status mda, mab generation is enabled (1) or masked (0). mxc mx bit control determines the value of the mx bit: 0: mx always 1.
preliminary data sheet w6694 passive usb - isdn s/t - controller - 25 - publication release date: march., 2000 revision 0.93 1: mx internally controlled according to monitor channel protocol. 8.3.3 monitor chan nel receive register mor read address 08h value after reset: ffh 7 6 5 4 3 2 1 0 8.3.4 monitor channel transmit register mox read/write address 09h value after reset: ffh 7 6 5 4 3 2 1 0 8.4 programmable io registers 8.4.1 pio input enable register pie read/write address 0ah value after reset: 00h 7 6 5 4 3 2 1 0 ie7 ie6 ie5 ie4 ie3 ie2 ie1 ie0 ie7 - 0 input enable for io pin 7 - 0. setting these bits enable corresponding io pin to become input pin. default is output pin. 8 .4.2 pio output register 1 po1 read/write address 0bh value after reset: 01h 7 6 5 4 3 2 1 0 om3_1 om3_0 om2_1 om2_0 om1_1 om1_0 om0_1 om0_0 omn_1 - 0 output mode of io pin n (n=3..0). setting corresponding bits drive output pin with different output mode. possible modes are: 00: always low 01: 0.5 second high/low cycle 10: 1 second high/low cycle 11: always high these bits have no effect on input pin.
preliminary data sheet w6694 passive usb - isdn s/t - controller - 26 - publication release date: march., 2000 revision 0.93 8.4.3 pio output register 2 po2 read/write address 0ch value after reset: 00h 7 6 5 4 3 2 1 0 om7_1 om7_0 om6_1 om6_0 om5_1 om5_0 om4_1 om4_0 omn_1 - 0 output mode of io pin n (n=7..4). 8.4.4 pio data register pdata read address 0dh value after reset: 00h 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 d7 - 0 read data of io pins 7 - 0 the corre sponding bits are the present values of io pins 7 - 0 (low=0, high=1). 8.5 b channel switch registers 8.5.1 layer1 b1 receiver select register l1b1rs read/write address 0eh value after reset: 04h 7 6 5 4 3 2 1 0 0 0 0 0 0 rs2 rs1 rs0 rs2 - 0 receiver s elect these bits select the source where layer 1 b1 channel will receive data from. possible values are: 000 (0): receive from pcm1 001 (1): receive from pcm2 010 (2): receive from layer1 b1 100 (4): receive from usb b1 8.5.2 layer1 b2 receiver select register l1b2rs read/write address 0fh value after reset: 05h 7 6 5 4 3 2 1 0 0 0 0 0 0 rs2 rs1 rs0 rs2 - 0 receiver select these bits select the source where layer 1 b2 channel will receive data from. possible values are: 000 (0): receive from pcm1 001 (1): receive from pcm2 011 (3): receive from layer1 b2 101 (5): receive from usb b2
preliminary data sheet w6694 passive usb - isdn s/t - controller - 27 - publication release date: march., 2000 revision 0.93 8.5.3 usb b1 receiver select register usbb1rs read/write address 10h value after reset: 02h 7 6 5 4 3 2 1 0 0 0 0 0 0 rs2 rs1 rs0 rs2 - 0 receiver select these bi ts select the source where usb b1 channel will receive data from. possible values are: 000 (0): receive from pcm1 001 (1): receive from pcm2 010 (2): receive from layer1 b1 100 (4): receive from usb b1 8.5.4 usb b2 receiver select register usbb2rs re ad/write address 11h value after reset: 03h 7 6 5 4 3 2 1 0 0 0 0 0 0 rs2 rs1 rs0 rs2 - 0 receiver select these bits select the source where usb b2 channel will receive data from. possible values are: 000 (0): receive from pcm1 001 (1): receive from pc m2 011 (3): receive from layer1 b2 101 (5): receive from usb b2 8.5.5 pcm1 receiver select register pcm1rs read/write address 12h value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 epcm rs2 rs1 rs0 epcm enable pcm transmit/receive 0: disable data trans mit/receive to/from pcm port. the frame synchronization clock is held low. the bit synchronization clock is low if both pcm ports are disabled. 1: enable data transmit/receive to/from pcm port. the frame synchronization clock is active. the bit synchr onization clock is active. rs2 - 0 receiver select these bits select the source where pcm1 channel will receive data from. possible values are: 000 (0): receive from pcm1 001 (1): receive from pcm2 010 (2): receive from layer1 b1 100 (4): receive from u sb b1
preliminary data sheet w6694 passive usb - isdn s/t - controller - 28 - publication release date: march., 2000 revision 0.93 8.5.6 pcm2 receiver select register pcm2rs read/write address 13h value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 epcm rs2 rs1 rs0 epcm enable pcm transmit/receive 0: disable data transmit/receive to/from pcm port. the frame synchronization cl ock is held low. the bit synchronization clock is held low if both pcm ports are disabled. 1: enable data transmit/receive to/from pcm port. the frame synchronization clock is active. the bit synchronization clock is active. rs2 - 0 receiver select thes e bits select the source where pcm2 channel will receive data from. possible values are: 000 (0): receive from pcm1 001 (1): receive from pcm2 011 (3): receive from layer1 b2 101 (5): receive from usb b2 9. electrical charac teristics 9.1 absolute m aximum rating parameter symbol limit values unit voltage on any pin with respect to ground v s - 0.4 to v dd +0.4 v ambient temperature under bias t a 0 to 70 c maximum voltage on v dd v dd 6 v 9.2 power supply parameter symbol min typ max unit remarks 5 v input voltage v dd 4.75 5.0 5.25 v pins vdd1, vdd21, vdd22, vdd23, vddu 3.3v regulator output v dd3 3.3 v pins vdd3i, vdd3 analog ground v ssa 0 v pins vss1 digital ground v ssd 0 v pins vss21, vss22, vss23, vssu
preliminary data sheet w6694 passive usb - isdn s/t - controller - 29 - publication release date: march., 2000 revision 0.93 9.3 dc characteristics t a =0 to 70 c; v dd =5 v 5 %, v ssa =0 v, v ssd =0 v parameter symbol min max unit test conditions remarks low input voltage v il - 0.4 0.8 v high input voltage v ih 2.0 v dd +0.4 v low output voltage v ol 0.4 v i ol = 12 ma high output voltage v oh 2.4 v powe r supply current: suspended i cc ma v dd =5v, s/t layer 1 in state ? f3 deactivated without clock ? , usb in suspended mode power supply current: activated i cc ma v dd =5v, s/t layer 1 in state ? f7 activated ? , usb is configured and active absolute value o f output pulse amplitude (v sx2 - v sx1 ) v x 2.03 2.10 2.31 2.39 v v r l =50 w 1) r l =400 w 1) sx1,2 transmitter output current i x 7.5 13.4 ma r l =5.6 w 1) sx1,2 transmitter output impedence r x 30 23 k w w inactive or during binary one during binary zero (r l =50 w ) sx1,2 note : 1) due to the transformer, the load resistance seen by the circuit is four times r l . capacitances of isdn pins t a =25 c, v dd = 5 v 5 %, v ssa = 0v, v ssd =0v, fc=1 mhz, unmeasured pins grounded. parameter symbol min. max. unit remarks out put capacitance against v ssa c out 10 pf sx1,2 input capacitance c in 7 pf sr1,2 load capacitance c l 50 pf xtal1,2 recommended oscillator circuits xtal1 xtal2 7.68mhz c l 50pf c l c l xtal1 xtal2 external oscillator signal n.c. or
preliminary data sheet w6694 passive usb - isdn s/t - controller - 30 - publication release date: march., 2000 revision 0.93 crystal specifications parameter symbol values unit frequency f 7.680 mhz frequency calibr ation tolerance max. 100 ppm load capacitance c l max. 50 pf oscillator mode fundamental note : the load capacitance c l depends on the crystal specification. the typical values are 33 to 47 pf. external ocsillator input (xtal1) clock characteristics parameter min. max. duty cycle 1:2 2:1 9.4 preliminary switching characteristics 9.4.1 pcm interface timing pbck (1.536mhz) pfck1 pfck2 ptxd prxd 24 chs ch 1 ch 2 port1 port1 port2 port2 port1 port1 port2 po rt2
preliminary data sheet w6694 passive usb - isdn s/t - controller - 31 - publication release date: march., 2000 revision 0.93 note 1: these drawings are not to scale. note 2 : the frequency of pbck is 1536 khz which includes 24 channels o f 64 kbps data. the pfck1 and pfck2 are located at channel 1 and channel 2, each with a 8 x pbck duration. detailed pcm timing parameter parameter descriptions min. nominal max. remarks ta1 pbck pulse high 325 unit = ns ta2 pbck pulse low 195 325 455 ta3 frame clock asserted from pbck 20 ta4 ptxd data delay from pbck 20 ta5 frame clock deasserted from pbck 20 ta6 ptxd hold time from pbck 10 ta7 prxd setup time to pbck 20 ta8 prxd hold time from pbck 10 note : the pcm clocks are locked to the s/t receive clock. at every two or three pcm frame time (125 m s), pbck and pfck1, pfck2 may be adjusted by one local oscillator cycle (130 ns) in order to synchronize with s/t clock. this shift is made on th e low level time of pbck and the high level time is not affected. this introduces jitters on the pbck, pfck1 and pfck2 with jitter amplitude 260 ns (peak - to - peak) and jitter frequency about 2.67~4 khz. pbck pfck1 pfck2 ptxd prxd ta1 ta2 ta3 ta4 ta5 ta6 ta7 ta8
preliminary data sheet w6694 passive usb - isdn s/t - controller - 32 - publication release date: march., 2000 revision 0.93 9.4.2 serial eeprom timing para meter parameter descriptions min. max. remarks tb1 epsk low 2500 unit = ns tb2 epsk high 2500 tb3 epcs output delay 30 tb4 epsd output delay 30 tb5 epsd tri - state delay 30 tb6 epsd input setup time 30 tb7 epsd input hold time 30 a5 a4 a1 a0 ..... d15 d14 d1 d0 ....... tb1 tb2 tb3 tb3 tb4 tb4 tb5 tb7 tb6 epsk epcs epsdi

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